In high-speed data transmission applications over telephone twisted pair cable, the requirement for a low error rate is essential to the stable operation of the communications channel. When digital data is transmitted at a high rate over a telephone line, the main impairments are attenuation, dispersion and crosstalk noise. In addition, when signal transmission is fully duplex, the echo signal originating from the transmitter interferes with the data being received.
An example of a high speed data transmission application is the digital subscriber loop in the evolving Integrated Services Digital Network (ISDN).
The required data transmission rate over digital subscriber lines in the ISDN is 160 kbits/sec. To improve ISDN data transmission performance against the impairments mentioned above, the data to be transmitted is coded into a bandwidth-reducing format before it is transmitted.
Different modulation techniques can be employed to reduce the bandwidth of a transmitted signal. The modulation technique adopted in the United States by the American National Standard Institute (ANSI) for use over the digital subscriber line is called 2B1Q line coding. 2B1Q coding is a technique whereby a binary input sequence is transformed into a quaternary sequence by amplitude modulating pairs of bits in the binary stream of data.
According to the 2B1Q coding technique, successive pairs of binary data B=(0,1) are one-to-one mapped onto corresponding units of quaternary symbols Q=(-3, -1, +1, +3) and then transmitted as a corresponding voltage level at half the rate of the binary sequence. Therefore, an incoming binary data stream B with a bit rate of 160 kbit/sec is converted into a quaternary bit stream Q with a symbol rate of 80 kilo-symbols/sec and then transmitted. The conventional mapping rule from the binary data format to the 2B1Q data format is provided in Table 1 below.
TABLE 1 ______________________________________ Binary (B) Quaternary q.sub.0 q.sub.1 (Q) ______________________________________ 1 1 +1 1 0 +3 0 1 -1 0 0 -3 ______________________________________
The signal processing that is performed on a 2B1Q transmission in the data detection process is intended to remove echo interference in the received signal that is generated by the transmitter and to remove the distortion in the received signal itself. The former filtering task is referred to as echo cancellation and the latter is known as equalization.
Both echo cancellation and equalization filtering functions utilize a similar structure in that they can be performed by the same hardware configuration. One such configuration is the linear transversal filter.
A conventional linear transversal filter is shown in FIG. 1. The filter 10 of FIG. 1 performs the convolution between the transmitted signal, e.g. 2B1Q symbols q(n), where q(n) is chosen from the set (-3, -1, +1, +3) and n is a discrete time variable, and the filter's individual tap gain coefficients a.sub.j, to arrive at an output y(n) where ##EQU2##
As shown in FIG. 1, a conventional transversal filter 10 comprises a delay line 12 which is formed from unit delays 13 and is tapped at intervals corresponding to the symbol width. Each tap 14 along the delay line is connected through an amplifier 16 to a summing device 18 that provides the filter output y(n).
In practice, due to the slow time variability of the echo path or communications channel, and more importantly, due to the unknown initial values for the tap gain coefficients a.sub.j, an adaptive filter is required for echo cancellation and equalization.
An example of an algorithm which can be used to adapt the filter coefficients is the well known Least Mean Squares (LMS) algorithm.
A hardware implementation of the filter of FIG. 1 is shown in FIG. 2. The following notation is used in connection with the explanation of FIG. 2. For each coefficient a.sub.j, m(a.sub.j) is the magnitude of a.sub.j and s(a.sub.j) is the sign of a.sub.j. In addition, it should be noted (see Table 1) that for each quaternary symbol q(n-j), the first bit of the binary representation q.sub.o indicates the sign of the symbol and the second bit q.sub.1 represents the magnitude. Thus, as shown in Table 1, a zero in the q.sub.o position indicates a negative sign and a one in the q.sub.o position indicates a positive sign. Similarly, a zero in the q.sub.1 position indicates the magnitude is "3" and a one in the q.sub.1 position indicates the magnitude is "1".
The filter 10 of FIG. 2 performs the multiplications a.sub.j q(n-j) and then sums these products to get an output y(n). Each product is (+1)a.sub.j, (+3)a.sub.j, (-1)a.sub.j or (-3)a.sub.j. To obtain these products, the filter 10 of FIG. 2 comprises a left shift register 22 and a latch 24. The outputs of the shift register 22 and latch 24 are added by the adder 16. m(a.sub.j) is inputted into the shift register 22 and the latch 24. If q.sub.1 =1, then the output of the latch 24 is zero and the shift register 22 shifts by zero places. The coefficient magnitude m(a.sub.j) is then outputted by the adder 16. If q.sub.1 =0, then the output of the latch 24 equals its input, i.e., m(a.sub.j), and the output of the shift register 22 is its input shifted one place to the left, i.e, 2 m(a.sub.j). The adder 16 adds the latch output and the shift register output to obtain 3 m(a.sub.j).
The exclusive-or-gate (XOR) 18 receives s(a.sub.j) and q.sub.o as inputs. In response, the gate 18 outputs a one bit control signal P.sub.j to adder/subtractor unit 20. If P.sub.j =1, the unit 20 is placed in an addition mode. If P.sub.j =0, the unit 20 is placed in a subtraction mode. The output of the adder 16 is then added to or subtracted from the accumulated value of all previous products stored in the accumulator 23. In this manner, the sum is obtained. ##EQU3##
The weakness of the filter of FIGS. 1 and 2 is the difficulty of performing the multiplication by three.
A more efficient filter for use with 2B1Q symbols is disclosed in U.S. Pat. No. 4,926,472. This filter eliminates the need for multiplication by three.
According to the preferred technique, the 2B1Q signal Q=(-3, -1, +1, +3) is shifted one bit to the left to generate a corresponding shifted symbol alphabet S=(-2, 0, +2, +4). The shifted symbols are then processed through a transversal filter to produce the output y(n), where ##EQU4##
The output y(n) results from the convolution between the shifted symbols s(n) and the tap coefficients a.sub.j.
By shifting the conventionally coded 2B1Q symbols to provide a new symbol alphabet comprising powers-of-two numbers, the multiplication operation in the convolution summation involves only 2a.sub.j terms, rather than the potential .+-.3a.sub.j terms normally associated with 2B1Q signal processing.
A filter which uses this technique is shown in FIG. 3. The filter 30 of FIG. 3 comprises the conventional transversal filter delay line 32 which is formed from unit delays 33, and which is tapped at intervals 34 corresponding to the symbol width. Each tap 34 along the delay line is connected through an amplifier 36 with weight a.sub.j to a summing device 38 that provides the filter output. The filter includes a DC tap 39 with a fixed input signal level of one with a tap weight d=.SIGMA.a.sub.j to compensate for the symbol shift.
A hardware implementation of the filter of FIG. 3 is illustrated in FIG. 4. In the discussion pertaining to FIG. 3, s.sub.o, s.sub.1 indicate the bits of the shifted symbols s(n-j).
The filter 40 of FIG. 4 includes the shift register 42. For each coefficient a.sub.j, the quantity m(a.sub.j) is placed in the shift register 42. The multiplexer 34 receives the bits s.sub.o and s.sub.1 for each shifted symbol s(n-j).
Depending on s.sub.0 and s.sub.1, the multiplexer 34 outputs a signal requiring a two place left shift corresponding to multiplication by 4, no shift corresponding to no multiplication, or a one place left shift corresponding to multiplication by 2 or -2. The Exclusive-or-gate 18, addition/subtraction unit 20, and accumulator 23 operate in the same manner as in the filter 10 of FIG. 2 to accumulate the filter output. A multiplexer is provided so that a term d=.SIGMA.a.sub.j to compensate for the symbol shift may be added to the value in the accumulator 23 to obtain the final filter output y(n).
While the filter 30 of FIGS. 3 and 4 eliminates the need for multiplication by three, the filter 30 of FIGS. 3 and 4 suffers from a disadvantage in that the symbol shifting requires a modification of the conventional LMS algorithm which is used to adapt the filter coefficients. In particular, the need to update the offset d=.SIGMA.a.sub.j in each cycle increases the calculation requirements of the LMS algorithm and also alters the convergence pattern of the LMS algorithm.
In view of the foregoing, it is an object of the invention to provide a filter for 2B1Q symbols which overcomes the disadvantages of the prior art filters discussed above. In particular, it is an object of the invention to provide a 2B1Q filter which requires a minimum of hardware (including no multiplexers or other structures for multiplying by three) and a minimum number of operations to obtain the filter output.